Booth Recoded Multiplier

2002: For my final project in 6.371 (Introduction to VLSI Systems), Benjamin Walker, Jeremy Walker and I designed and implemented an 8x8 bit booth recoded multiplier. Logic design, layout and verification were done for three different versions of the multiplier: i) static CMOS, ii) pipelined static CMOS, and iii) dual-rail domino.

Project proposal: pdf
Project webpage: html